`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/10/23 15:21:30
// Design Name: 
// Module Name: maindec
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module maindec(
	input wire[5:0] op,
    input wire[5:0] funct, 
	output wire memtoreg,memwrite,
	output wire branch,alusrc,
	output wire regdst,regwrite,
	output wire jump,
	output wire signextend,
	output wire hilosel,
	output wire hilo_reg,
	output wire[1:0] hilowrite,
	output wire reg_alu_sel,
	output wire[7:0] alucontrol
    );
	reg[20:0] controls;
	assign {regwrite,regdst,alusrc,branch,memwrite,memtoreg,jump,signextend,hilosel,hilo_reg,hilowrite,reg_alu_sel,alucontrol} = controls;
	always @(*) begin
		case (op)
//			6'b000000:controls <= 9'b110000010;//R-TYRE
//			6'b100011:controls <= 9'b101001000;//LW
//			6'b101011:controls <= 9'b001010000;//SW
//			6'b000100:controls <= 9'b000100001;//BEQ
//			6'b001000:controls <= 9'b101000000;//ADDI
//			6'b000010:controls <= 9'b000000100;//J
//			default:  controls <= 9'b000000000;//illegal op
            6'b001100:controls <= 21'b1010000_1_0000_0_00010001;  //andi
            6'b001110:controls <= 21'b1010000_1_0000_0_00010011;  //xori
            6'b001111:controls <= 21'b1010000_1_0000_0_00010101;  //lui
            6'b001101:controls <= 21'b1010000_1_0000_0_00010010;  //ori
            6'b001000:controls <= 21'b1010000_0_0000_0_01000011;  //addi
            6'b001001:controls <= 21'b1010000_0_0000_0_01000010;  //addiu
            6'b001010:controls <= 21'b1010000_0_0000_0_01001101;  //slti
            6'b001011:controls <= 21'b1010000_0_0000_0_01001110;  //sltiu
            default: case(funct)
                6'b100100: controls <= 21'b1100000_0_0000_0_00010001;  //and
                6'b100101: controls <= 21'b1100000_0_0000_0_00010010;  //or
                6'b100110: controls <= 21'b1100000_0_0000_0_00010011;  //xor
                6'b100111: controls <= 21'b1100000_0_0000_0_00010100;  //nor
                6'b000000: controls <= 21'b1100000_0_0000_0_00100001;  //sll
                6'b000010: controls <= 21'b1100000_0_0000_0_00100010;  //srl
                6'b000011: controls <= 21'b1100000_0_0000_0_00100011;  //sra
                6'b000100: controls <= 21'b1100000_0_0000_0_00100100;  //sllv
                6'b000110: controls <= 21'b1100000_0_0000_0_00100110;  //srlv
                6'b000111: controls <= 21'b1100000_0_0000_0_00100111;  //srav
                6'b010000: controls <= 21'b1100000_0_1100_0_00000000;  //mfhi
                6'b010010: controls <= 21'b1100000_0_0100_0_00000000;  //mflo
                6'b010001: controls <= 21'b0100000_0_0010_0_00000000;  //mthi
                6'b010011: controls <= 21'b0100000_0_0001_0_00000000;  //mtlo
                6'b100000: controls <= 21'b1100000_0_0000_0_01000001;  //add
                6'b100001: controls <= 21'b1100000_0_0000_0_01000010;  //addu
                6'b100010: controls <= 21'b1100000_0_0000_0_01000101;  //sub
                6'b100011: controls <= 21'b1100000_0_0000_0_01000100;  //subu
                6'b101010: controls <= 21'b1100000_0_0000_0_01001101;  //slt
                6'b101011: controls <= 21'b1100000_0_0000_0_01001110;  //sltu
                6'b011000: controls <= 21'b0100000_0_0011_1_01001011;  //mult
                6'b011001: controls <= 21'b0100000_0_0011_1_01001010;  //multu
                6'b011010: controls <= 21'b0100000_0_0011_1_01001001;  //div
                6'b011011: controls <= 21'b0100000_0_0011_1_01001000;  //divu
                default: controls <= 21'b0;
            endcase
		endcase
	end
endmodule